The present invention relates to processor branch prediction generally and, more particularly, to a method and/or architecture for implementing branch misprediction recovery for an instruction cache memory.
Modern pipelined processors generally incorporate some form of branch prediction to maximize performance when encountering a branch instruction in a stream of instructions. A correct branch prediction of taking a branch will result in a modest delay to a pipeline of the processor while the target branch instruction is fetched from a main memory. A branch misprediction of taking the branch can result in unnecessary delays in the pipeline. In particular, if the branch misprediction occurs early in an instruction cache line fetch operation, the pipeline is stalled while the instruction cache line fetch operation is completed. Once the instruction cache line fetch operation is completed, the pipeline stall is removed and a request for the next instruction in the branch is made to the main memory. Consequently, evaluation of the branch prediction is not performed until after the instruction cache line fetch operation has completed and the pipeline stall has been removed.
Stalling the pipeline during instruction cache line fetching introduces unnecessary delays in the event of a branch misprediction. Since the branch should not have been taken, there is no reason to wait for the current instruction cache line fetch operation to complete. It would be desirable to execute the next sequential instruction immediately if the next sequential instruction has already been copied into an instruction cache memory of the processor. Overall processor performance would be improved if the unnecessary stalls following a mispredicted branch taken were reduced or eliminated.
The present invention concerns a method and/or an architecture for recovering from a branch misprediction in a processor. The method may comprise the steps of (A) evaluating a branch prediction for a branch instruction, (B) pausing an instruction cache line fetch in response to the branch instruction, and (C) resuming the instruction cache line fetch in response to a branch misprediction.
The objects, features and advantages of the present invention include (i) providing a method and/or architecture for a processor to recover from a branch misprediction of taking the branch, and/or (ii) improving a performance of the processor by eliminating or reducing a number of stall cycles following the branch misprediction.